Embodiments of the present invention relate to a semiconductor device and a method for forming the same, and more particularly to a semiconductor device including a contact plug and a method for forming the same.
Recently, most electronic appliances comprise a semiconductor device. Semiconductor devices include electronic elements such as transistors, resistors and capacitors. These electronic elements are designed to perform electronic functions, and are integrated on a semiconductor substrate. For example, an electronic appliance, such as a computer or a digital camera, includes a memory chip for storing information and a processing chip for controlling information. The memory chip and the processing chip include electronic elements integrated on a semiconductor substrate.
Semiconductor devices must increase in integration degree in order to satisfy consumer demands for superior performance and low prices. Such an increase in the integration degree of a semiconductor device entails a reduction in a design rule, causing patterns of a semiconductor device to be increasingly reduced. Although an entire chip area is increased, a cell area, where patterns of a semiconductor device are actually formed, is decreased. Accordingly, since a greater number of patterns should be formed in a limited cell area in order to achieve a desired memory capacity, there is a need for formation of microscopic (fine) patterns having a reduced minimum pattern size.
Meanwhile, as the minimum pattern size of such microscopic patterns is gradually reduced, a hole pattern for connecting upper and lower conductive lines to each other is significantly affected by a design rule, as compared to line and space patterns. In more detail, an increase in the integration degree of a semiconductor device causes a reduction in a contact hole size and the distance between the contact hole and its neighboring conductive line. Consequently, this causes an increase in an aspect ratio of the contact hole, that is, a ratio of a depth with respect to a diameter of the contact hole. In a highly integrated semiconductor device having multilayered conductive lines, a contact forming process may require precise and strict mask alignment, which entails a reduction in process tolerance, making a patterning process difficult.
Meanwhile, a bit line contact plug or a storage node contact plug is generally formed of polysilicon. If polysilicon is employed as material filling in the contact plugs in a highly-integrated semiconductor device, a void is likely to form in the contact plug. When a heat process is performed in a subsequent process, the size of the void increases.
The void increases the resistance of a contact plug and deteriorates semiconductor device characteristics. As a result, a method for preventing the void from forming so as to reduce resistance of a contact plug is needed.